Embodiments of the inventive concept relate to semiconductor devices and, more particularly, to semiconductor devices having through-vias and methods for fabricating the same.
Generally, for electrically insulating a through silicon via (TSV) from a substrate, a via-insulating layer may be formed by a chemical vapor deposition (CVD) process and a bottom surface of the substrate may be recessed such that the TSV protrudes therefrom. If the via-insulating layer is etched during this process, the TSV may be exposed. The exposed portion of the TSV may function as a contamination or a particle-source, such that errors of subsequent processes may occur.